A static random access memory (SRAM) includes a memory array made up of memory cells in an arrangement of rows and columns. A single data bit in binary form can be stored in each memory cell. Each row includes a word line that interconnects memory cells on the row with a common control signal. Similarly, each column includes a complementary pair of bit lines coupled to at most one cell in each row. The word and bit lines can be controlled to individually access each memory cell of the memory array.
An asynchronous SRAM does not respond to a clock signal. Instead, an asynchronous SRAM responds to an address change. An address transition detect (ATD) circuit detects whether there has been a transition made on an address line. The ATD circuit indicates selection of a memory cell in a row different from a previously selected memory cell, and generates an address transition detect (ATD) pulse indicating an address change. Address transition detection is only necessary for a row address transition because precharging the bit lines is not necessary for a column address change. However, the ATD circuit may be applied to all addresses and/or control signals.
There is a bit line precharge circuit for each column of bit line pairs in the SRAM. Before data can be read out of the selected memory cell, the bit line pair associated with the selected memory cell must be precharged. Each time a subsequent memory cell on a new column is selected, the bit line pair for that corresponding memory cell must also be precharged before the data value can be read.
The bit line precharge circuits effectively connect the bit line pairs to a reference supply voltage. The reference supply voltage is typically midway between the high and low logic levels of the memory device. Conventionally, bit line pairs are precharged to one-half of the power supply voltage. If the bit line pairs were not precharged, a voltage difference present on the bit line pair may inadvertently discharge a value into the selected memory cell due to the high capacitive load caused by the other memory cells connected to the same bit line pair.
Currently, upon detection of a row address transition, the ATD pulse is globally applied to all the bit line precharge circuits 22 in an SRAM device 30, as shown in FIG. 1. An address input circuit 24 receives an address signal and provides the signal to the ATD circuit 20. The ATD circuit 20 detects whether there has been a transition in the address signal from a previously received address signal, and if so, generates an ATD pulse. The ATD pulse is then applied globally to all of the bit line precharge circuits 22.
The term global in this illustration means that all the bit line precharge circuits, collectively represented by the single block 22, receive the ATD pulse for initiating precharging of their respective bit line pairs. As a result, all the bit line pairs are simultaneously precharged, which is typically to one-half of the power supply voltage. Simultaneously precharging all the bit line precharge circuits 22 causes the SRAM 30 to dissipate unnecessary power since data can only be read out of one memory cell at a time during a bit line precharge cycle. Another disadvantage of simultaneously precharging all the bit line precharge circuits 22 is that large voltage spikes occur, which tends to generate noise and cause the voltage level at the power pad to drop due to package (pin) inductance.
U.S. Pat. No. 4,969,125 to Caerula, et al., hereinafter referred to as the '125 Patent and is hereby incorporated by reference, discloses an SRAM device 39 having a segmented memory array that eliminates the problem of large current spikes by limiting the number of precharge circuits that are simultaneously precharged in response to the ATD pulse, as shown in FIG. 2. The memory array 40 is divided into a plurality of memory array segments 42a-42n, with each memory array segment containing a portion of all the bit line pairs. Each memory array segment 42a-42n has a bit line precharge circuit 44 for precharging the bit line pairs associated therewith so that when the ATD circuit 46 generates the ATD pulse, only the bit line pairs associated with a selected memory array segment 42a are precharged. The segmented precharged driver 48 corresponding to the memory array segment 42a containing the memory cell to be read is selected for precharging the bit line precharged circuit 44.
A drawback of the segmented SRAM device 39 disclosed in the '125 Patent is that the ATD pulse is still distributed to all the segmented precharged drivers 48. This causes the SRAM 39 to dissipate unnecessary power since only one of the segmented precharge drivers 48 is actually selected for providing the ATD pulse to the memory array 42a. In addition, interfacing the ATD circuit 46 with each segmented precharge driver 48 causes the output of the ATD circuit 46 to see a large capacitive load. A large capacitive load slows down the rise and fall time of the ATD pulse and its propagation to the segmented precharge drivers 48. Consequently, a delayed and loosely controlled ATD pulse slows down the access time of the SRAM device 39.
To better control the ATD pulse in the '125 Patent, each address input has a true signal path and a complement signal path connected to respective address pulse generators. In other words, there is an address pulse generator for detecting a rising address transition and a separate address pulse generator for detecting a falling address transition.